Double data rate: Difference between revisions
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In [[computing]], a [[computer bus]] operating with '''double data rate''' transfers data on both the rising and falling edges of the [[clock signal]], effectively nearly doubling the data transmission rate without having to deal with the additional problems of [[timing skew]] that increasing the number of data lines would introduce. This is also known as '''double pumped''', '''dual-pumped''', and '''double transition'''. | In [[computing]], a [[computer bus]] operating with '''double data rate''' transfers data on both the rising and falling edges of the [[clock signal]], effectively nearly doubling the data transmission rate without having to deal with the additional problems of [[timing skew]] that increasing the number of data lines would introduce. This is also known as '''double pumped''', '''dual-pumped''', and '''double transition'''. It is frequently abbreviated as "DDR". | ||
This technique has been used for the [[Front side bus]], [[SCSI#Ultra-3|Ultra-3 SCSI]], the [[Accelerated Graphics Port]] (AGP) bus, [[DDR SDRAM]], and the [[HyperTransport]] version 3.0 bus. | This technique has been used for the [[Front side bus]] (FSB), [[SCSI#Ultra-3|Ultra-3 SCSI]], the [[Accelerated Graphics Port]] (AGP) 2x bus, [[DDR SDRAM]], and the [[HyperTransport]] version 3.0 bus. [[Quadruple data rate]] (QDR) has replaced DDR in many Front side buses (including in [[Intel]] [[x86]] processors). However, QDR is currently | ||
An alternative to double or [[Quadruple data rate|quad pumping]] is to make the link [[Self-clocking signal|self-clocking]]. This tactic was chosen by [[InfiniBand]] and [[PCI Express]]. | An alternative to double or [[Quadruple data rate|quad pumping]] is to make the link [[Self-clocking signal|self-clocking]]. This tactic was chosen by the [[InfiniBand]] and [[PCI Express]] buses. | ||
It is often difficult to know how to refer to the speed of a double-pumped bus. Discussing the raw bandwidth of a bus is less ambiguous than comparing clock speed and transfers per second as this also takes into account the width of the bus: thus [[DDR SDRAM]] that runs on a clock signal of 100 MHz, with data transfer the same as [[SDR SDRAM]] running at about 200 MHz, is called DDR-200 and PC-1600, referring to the [[peak bandwidth]]. However, this number does not take into account the bus protocol overhead or [[Latency|latencies]], both of which can reduce the effective bandwidth of a bus to a fraction of the raw bandwidth. | It is often difficult to know how to refer to the speed of a double-pumped bus. Discussing the raw bandwidth of a bus is less ambiguous than comparing clock speed and transfers per second as this also takes into account the width of the bus: thus [[DDR SDRAM]] that runs on a clock signal of 100 MHz, with data transfer the same as [[SDR SDRAM]] running at about 200 MHz, is called DDR-200 and PC-1600, referring to the [[peak bandwidth]]. However, this number does not take into account the bus protocol overhead or [[Latency|latencies]], both of which can reduce the effective bandwidth of a bus to a fraction of the raw bandwidth. In RAM, the "normal" clock rate is often used. RAM labelled as DDR2-800 runs at 800 MHz, while processors and chipsets commonly refer to their buses by the "doubled" clock speed rating. | ||
While a double-pumped bus can nearly double peak bandwidth | While a double-pumped bus can nearly double peak bandwidth it does nothing for [[latency (engineering)|latency]], because it takes the same amount of time for the first "word" to arrive from memory. By contrast, doubling the speed of the bus reduces latency, because the individual bits of data move across the bus faster. However, doubling the clock speed of a bus is a difficult and expensive engineering challenge. | ||
== See also == | == See also == | ||
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==References== | ==References== | ||
[http://arstechnica.com/articles/paedia/cpu/bandwidth-latency.ars "Understanding Bandwidth and Latency" by Jon Stokes] | [http://arstechnica.com/articles/paedia/cpu/bandwidth-latency.ars "Understanding Bandwidth and Latency" by Jon Stokes] | ||
[http://safari.oreilly.com/0596003536/pchardnut2-CHP-5-SECT-2 "PC Hardware in a Nutshell", O'Reilly Publishing] | |||
[[Category:Digital electronics]] | [[Category:Digital electronics]] | ||
[[Category:Computers Workgroup]] | [[Category:Computers Workgroup]] | ||
[[Category:CZ Live]] | [[Category:CZ Live]] | ||
Revision as of 02:41, 17 January 2007
In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal, effectively nearly doubling the data transmission rate without having to deal with the additional problems of timing skew that increasing the number of data lines would introduce. This is also known as double pumped, dual-pumped, and double transition. It is frequently abbreviated as "DDR".
This technique has been used for the Front side bus (FSB), Ultra-3 SCSI, the Accelerated Graphics Port (AGP) 2x bus, DDR SDRAM, and the HyperTransport version 3.0 bus. Quadruple data rate (QDR) has replaced DDR in many Front side buses (including in Intel x86 processors). However, QDR is currently
An alternative to double or quad pumping is to make the link self-clocking. This tactic was chosen by the InfiniBand and PCI Express buses.
It is often difficult to know how to refer to the speed of a double-pumped bus. Discussing the raw bandwidth of a bus is less ambiguous than comparing clock speed and transfers per second as this also takes into account the width of the bus: thus DDR SDRAM that runs on a clock signal of 100 MHz, with data transfer the same as SDR SDRAM running at about 200 MHz, is called DDR-200 and PC-1600, referring to the peak bandwidth. However, this number does not take into account the bus protocol overhead or latencies, both of which can reduce the effective bandwidth of a bus to a fraction of the raw bandwidth. In RAM, the "normal" clock rate is often used. RAM labelled as DDR2-800 runs at 800 MHz, while processors and chipsets commonly refer to their buses by the "doubled" clock speed rating.
While a double-pumped bus can nearly double peak bandwidth it does nothing for latency, because it takes the same amount of time for the first "word" to arrive from memory. By contrast, doubling the speed of the bus reduces latency, because the individual bits of data move across the bus faster. However, doubling the clock speed of a bus is a difficult and expensive engineering challenge.
See also
- Quadruple data rate
- DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM are all types of RAM utilizing DDR.
References
"Understanding Bandwidth and Latency" by Jon Stokes "PC Hardware in a Nutshell", O'Reilly Publishing